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M25PE40
4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout
Features

SPI bus compatible serial interface 4 Mbit Page-Erasable Flash memory Page size: 256 bytes - Page Write in 11 ms (typical) - Page Program in 0.8 ms (typical) - Page Erase in 10 ms (typical) SubSector Erase (4 Kbytes) Sector Erase (64 Kbytes) Bulk Erase (4 Mbits) 2.7 V to 3.6 V single supply voltage 50 MHz clock rate (maximum) Deep Power-down mode 1 A (typical) Electronic Signature - JEDEC standard two-byte signature (8013h) Software Write Protection on a 64 Kbyte sector basis Hardware Write Protection of the memory area selected using the BP0, BP1 and BP2 bits More than 100 000 Write cycles More than 20 year data retention Packages - ECOPACK(R) (RoHS compliant) SO8N (MN) 150 mils width SO8W (MW) 208 mils width
VFQFPN8 (MP) 6 x 5 mm (MLP8)

January 2007
Rev 7
1/59
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Contents
M25PE40
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Important note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (W) or Top Sector Lock (TSL) . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8.1 4.8.2 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Specific Hardware and Software protections . . . . . . . . . . . . . . . . . . . . . 15
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 6.2 6.3 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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M25PE40
Contents
6.4
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.1 6.4.2 6.4.3 6.4.4 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 29 Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Page Write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SubSector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7 8 9 10 11 12 13 14
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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List of tables
M25PE40
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Software protection truth table (Sectors 0 to 7, 64-Kbyte granularity) . . . . . . . . . . . . . . . . 16 Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Identification (RDID) Data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Protection modes (T9HX process only, see Important note on page 6) . . . . . . . . . . . . . . . 27 Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Lock Register In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Device status after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 AC characteristics (25 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 AC characteristics (33 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 AC characteristics (50 MHz operation, T9HX (0.11m) process) . . . . . . . . . . . . . . . . . . . 50 Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Timings after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead 6 x 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . 55 SO8W - 8 lead Plastic Small Outline, 208 mils body width, package mechanical data . . . 56 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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M25PE40
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Logic diagram - previous T7X process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic diagram - new T9HX process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Identification (RDID) instruction sequence and Data-out sequence . . . . . . . . . . . . . 23 Read Status Register (RDSR) instruction sequence and Data-out sequence . . . . . . . . . . 25 Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Data Bytes (READ) instruction sequence and Data-out sequence . . . . . . . . . . . . . . 28 Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and Data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read Lock Register (RDLR) instruction sequence and data-out Sequence. . . . . . . . . . . . 30 Page Write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Page Erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SubSector Erase (SSE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Release from Deep Power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 41 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead 6 x 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 55 SO8W - 8 lead Plastic Small Outline, 208 mils body width, package outline. . . . . . . . . . . 56
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Description
M25PE40
1
Description
The is a 4 Mbit (512Kb x 8 bit) Serial Paged Flash memory accessed by a high speed SPIcompatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle. The memory is organized as 8 sectors that are further divided up into 16 subsectors each (128 subsectors in total). Each sector contains 256 pages and each subsector contains 16 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes. The memory can be erased a page at a time, using the Page Erase instruction, a subsector at a time, using the SubSector Erase instruction, a sector at a time, using the Sector Erase instruction or as a whole, using the Bulk Erase (BE) instruction.. The memory can be Write Protected by either Hardware or Software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 64 Kbytes (sector granularity). In order to meet environmental requirements, ST offers the in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Important note
This datasheet details the functionality of the devices, based on the previous T7X process or based on the current T9HX process. Delivery of parts in T9HX process starts from July 2007.
What are the changes?
The in T9HX process offers the following additional features:

the whole memory array is partitioned into 4-Kbyte subsectors five new instructions: Write Status Register (WRSR), Write to Lock Register (WRLR), Read Lock Register (RDLR), 4-Kbyte SubSector Erase (SSE) and Bulk Erase (BE) Status Register: 4 bits can be written (BP0, BP1, BP2, SRWD) WP input (pin 3): Write protection limits are extended, depending on the value of the BP0, BP1, BP2, SRWD bits. The WP Write protection remains the same if bits (BP2, BP1, BP0) are set to (0, 0, 1). smaller die size allowing assembly into an SO8N package
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M25PE40
Description
Figure 1.
Logic diagram - previous T7X Figure 2. process
VCC
Logic diagram - new T9HX process
VCC
D C S TSL Reset M25PE40
Q
D C S W Reset M25PE40
Q
VSS
AI09704C
VSS
AI13781
Table 1.
Signal names
Function Serial Clock Serial Data Input Serial Data Output Chip Select Top Sector Lock or Write Protect Reset Supply Voltage Ground Input Input Output Input Input Input Direction
Signal name C D Q S TSL or W(1) Reset VCC VSS
1. In the previous T7X process the pin is a Top Sector Lock input whereas in the new T9HX process, the pin is a Write Protect input (see Figure 1 and Figure 2).
Figure 3.
VFQFPN and SO connections
M25PE40 S Q TSL or W VSS 1 2 3 4 8 7 6 5 VCC Reset C D
AI09703d
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Section 12: Package mechanical for package dimensions, and how to identify pin-1.
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Signal description
M25PE40
2
2.1
Signal description
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Reset (Reset)
The Reset (Reset) input provides a hardware reset for the memory. When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output is high impedance. Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost.
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M25PE40
Signal description
2.6
Write Protect (W) or Top Sector Lock (TSL)
The Write Protect function is available in the T9HX process only (see Important note on page 6). The Write Protect (W) input is used to freeze the size of the area of memory that is protected against write, program and erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register. See Section 6.4: Read Status Register (RDSR) for a description of these bits).
The Top Sector Lock function is available in the T7X process only (see Important note on page 6). The input signal sets the device in the Hardware Protected mode, when Top Sector Lock (TSL) is connected to VSS, causing the top 256 pages (upper addresses) of the memory to become read-only (protected from write, program and erase operations). When Top Sector Lock (TSL) is connected to VCC, the top 256 pages of memory behave like the other pages of memory.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
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SPI modes
M25PE40
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Bus master and memory devices on the SPI bus
VSS VCC R SDO SPI Interface with SDI (CPOL, CPHA) = SCK (0, 0) or (1, 1) CQD SPI Bus Master R CS3 CS2 CS1 S W HOLD or TSL S W HOLD or TSL S HOLD W or TSL SPI Memory Device VCC VSS R SPI Memory Device CQD VCC VSS R SPI Memory Device CQD VCC VSS
Figure 4.
AI13558
1. The Write Protect or Top Sector Lock (W or TSL) signal should be driven, High or Low as appropriate.
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in Figure 4) ensure that the is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). The typical value of R is 100 k assuming that the time constant R*Cp (Cp = parasitic capacitance of the bus , line) is shorter than the time during which the Bus Master leaves the SPI bus in high impedance.
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M25PE40
SPI modes Example: Cp = 50 pF, that is R*Cp = 5 s <=> the application must ensure that the Bus Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 s. Figure 5.
CPOL CPHA C
SPI modes supported
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
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Operating features
M25PE40
4
4.1
Operating features
Sharing the overhead of modifying data
To write or program one (or more) data bytes, two instructions are required: Write Enable (WREN), which is one byte, and a Page Write (PW) or Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal cycle (of duration tPW or tPP). To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to 256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, provided that they lie in consecutive addresses on the same page of memory.
4.2
An easy way to modify data
The Page Write (PW) instruction provides a convenient way of modifying data (up to 256 contiguous bytes at a time), and simply requires the start address, and the new data in the instruction sequence. The Page Write (PW) instruction is entered by driving Chip Select (S) Low, and then transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte, and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data bytes are written to the data buffer, starting at the address given in the third address byte (A7-A0). When Chip Select (S) is driven High, the Write cycle starts. The remaining, unchanged, bytes of the data buffer are automatically loaded with the values of the corresponding bytes of the addressed memory page. The addressed memory page then automatically put into an Erase cycle. Finally, the addressed memory page is programmed with the contents of the data buffer. All of this buffer management is handled internally, and is transparent to the user. The user is given the facility of being able to alter the contents of the memory on a byte-by-byte basis. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few bytes (see Section 6.9: Page Write (PW) and Table 20: AC characteristics (50 MHz operation, T9HX (0.11m) process)).
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M25PE40
Operating features
4.3
A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be:

when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier Page Erase (PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available when the designer knows that the only changes involve resetting bits to 0 that are still set to 1. When this method is possible, it has the additional advantage of minimizing the number of unnecessary erase operations, and the extra stress incurred by each page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Section 6.10: Page Program (PP) and Table 20: AC characteristics (50 MHz operation, T9HX (0.11m) process)).
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (tPW, tPP, tPE, or tSE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous cycle is complete.
4.5
Reset
An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition protection is provided by driving Reset (Reset) Low during the Power-on process, and only driving it High when VCC has reached the correct voltage level, VCC(min).
4.6
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write). The device then goes in to the Standby Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Deep Powerdown (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until the Release from Deep Power-down instruction is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.
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Operating features
M25PE40
4.7
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by using specific instructions. See Section 6.4: Read Status Register (RDSR) for a detailed description of the Status Register bits.
4.8
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the features the following data protection mechanisms:
4.8.1
Protocol-related protections

Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - - - - - - - Power-up Reset (RESET) driven Low Write Disable (WRDI) instruction completion Page Write (PW) instruction completion Page Program (PP) instruction completion Write to Lock Register (WRLR) instruction completion Page Erase (PE) instruction completion SubSector Erase (SSE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion
The Reset (Reset) signal can be driven Low to freeze and reset the internal logic. For the specific cases of Program and Write cycles, the designer should refer to Section 6.5: Write Status Register (WRSR), Section 6.9: Page Write (PW), Section 6.10: Page Program (PP), Section 6.12: Page Erase (PE), Section 6.14: Sector Erase (SE), and Section 6.13: SubSector Erase (SSE), and to Table 12: Device status after a Reset Low pulse. In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions while the device is not in active use.
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M25PE40
Operating features
4.8.2
Specific Hardware and Software protections
The features a Hardware Protected mode, HPM, and two Software Protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. They are described below:
HPM
HPM in T7X process (see Important note on page 6): The Hardware Protected mode (HPM) is entered when Top Sector Lock (TSL) is driven Low, causing the top 256 pages of memory to become read-only. When Top Sector Lock (TSL) is driven High, the top 256 pages of memory behave like the other pages of memory and the protection depends on the Block Protect bits (see SPM2 below).
HPM in T9HX process (see Important note on page 6): The Hardware Protected mode (HPM) is used to write-protect the non-volatile bits of the Status Register (that is, the Block Protect bits, BP2, BP1 and BP0, and the Status Register Write Disable bit, SRWD). HPM is entered by driving the Write Protect (W) signal Low with the SRWD bit set to High. This additional protection allows the Status Register to be hardware-protected. (see also Section 6.4.4: SRWD bit)
SPM1 and SPM2
The first Software Protected mode (SPM1) is managed by specific Lock Registers assigned to each 64-Kbyte sector. The Lock Registers can be read and written using the Read Lock Register (RDLR) and Write to Lock Register (WRLR) instructions. In each Lock Register two bits control the protection of each sector: the Write Lock Bit and the Lock Down Bit. - Write Lock Bit: The Write Lock Bit determines whether the contents of the sector can be modified (using the Write, Program or Erase instructions). When the Write Lock Bit is set, `1', the sector is write protected - any operations that attempt to change the data in the sector will fail. When the Write Lock Bit is reset to `0', the sector is not write protected by the Lock Register, and may be modified. - Lock Down Bit: The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, `1', further modification to the Write Lock and Lock Down Bits cannot be performed. A reset, or power-up, is required before changes to these bits can be made. When the Lock Down Bit is reset, `0', the Write Lock and Lock Down Bits can be changed. The Write Lock Bit and the Lock Down Bit are volatile and their value is reset to `0' after a Power-Down or a Reset.
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Operating features Table 2.
M25PE40 Software protection truth table (Sectors 0 to 7, 64-Kbyte granularity)
Protection status
Sector Lock Register Lock Down bit 0 0 1 1 Write Lock bit 0 1 0 1
Sector unprotected from Program/Erase/Write operations, Protection status reversible Sector protected from Program/Erase/Write operations, Protection status reversible Sector Unprotected from Program/Erase/Write operations, Sector Protection Status cannot be changed except by a Reset or Power-up. Sector Protected from Program/Erase/Write operations, Sector Protection Status cannot be changed except by a Reset or Power-up.
The second Software Protected mode (SPM2) uses the Block Protect (BP2, BP1, BP0, see Section 6.4.3)) bits to allow part of the memory to be configured as read-only. Protected area sizes
Memory content
Table 3.
Status Register content BP2 BP1 BP0 Bit Bit Bit 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 none Upper eighth (Sector 7) Protected area
Unprotected area All sectors(1) (eight sectors: 0 to 7) Lower seven-eighths (seven sectors: 0 to 6)
Upper quarter (two sectors: 6 and 7) Lower three-quarters (six sectors: 0 to 5) Upper half (four sectors: 4 to 7) All sectors (eight sectors: 0 to 7) All sectors (eight sectors: 0 to 7) All sectors (eight sectors: 0 to 7) All sectors (eight sectors: 0 to 7) Lower half (four sectors: 0 to 3) none none none none
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
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M25PE40
Memory organization
5
Memory organization
The memory is organized as:

2048 pages (256 bytes each) 524,288 bytes (8 bits each) 128 subsectors (32 Kbits, 4096 bytes each) 8 sectors (512 Kbits, 65536 bytes each) - - - programmed (bits are programmed from 1 to 0) erased (bits are erased from 0 to 1) written (bits are changed to either 0 or 1)
Each page can be individually:
The device is Page or Sector Erasable (bits are erased from 0 to 1). Table 4. Memory organization
Address Range 7F000h ... 70000h 6F000h ... 60000h 5F000h ... 50000h 4F000h ... 40000h 3F000h ... 30000h 2F000h ... 20000h 1F000h ... 10000h 7FFFFh ... 70FFFh 6FFFFh 60FFFh 5FFFFh 50FFFh 4FFFFh 40FFFh 3FFFFh 30FFFh 2FFFFh 20FFFh 1FFFFh 10FFFh ... ... ... ... ... ... 0 Sector Subsector 15 ... 4 3 2 1 0 Address Range 0F000h ... 04000h 03000h 02000h 01000h 00000h 0FFFFh 04FFFh 03FFFh 02FFFh 01FFFh 00FFFh ... 17/60
Sector Subsector 127 7 112 111 6 96 95 5 80 79 4 64 63 3 48 47 2 32 31 1 16 ... ... ... ... ... ... ...
Memory organization Figure 6.
Reset TSL or W S C D Q Control Logic High Voltage Generator
M25PE40 Block diagram
I/O Shift Register
Address Register and Counter
256 byte Data Buffer
Status Register
7FFFFh 6FFFFh Top 256 Pages can be made read-only by using the TSL pin(1)
Whole Memory Array can be made read-only on a 64 Kbyte basis through the Lock Registers
Y Decoder
00000h 256 bytes (Page Size) X Decoder
000FFh
AI13782
1. These features (in gray) are only available in the T7X process.
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M25PE40
Instructions
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed inTable 5 Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Read to Lock Register (RDLR) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Write (PW), Page Program (PP), Page Erase (PE), SubSector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Enable (WREN), Write Disable (WRDI), Write Status Register (WRSR), Write to Lock Register (WRLR), Deep Power-down (DP) or Release from Deep Power-down (RDP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle are ignored, and the internal Write cycle, Program cycle or Erase cycle continues unaffected.
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Instructions Table 5.
Instruction WREN WRDI RDID RDSR
(1)
M25PE40 Instruction set
Description Write Enable Write Disable Read Identification Read Status Register Write to Lock Register Write Status Register Read Lock Register Read Data Bytes One-byte Instruction code 0000 0110 0000 0100 1001 1111 0000 0101 1110 0101 0000 0001 1110 1000 0000 0011 0000 1011 0000 1010 0000 0010 1101 1011 0010 0000 1101 1000 1100 0111 1011 1001 1010 1011 06h 04h 9Fh 05h E5h 01h E8h 03h 0Bh 0Ah 02h DBh 20h D8h C7h B9h ABh Addr Dummy bytes bytes 0 0 0 0 3 0 3 3 3 3 3 3 3 3 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Data bytes 0 0 1 to 3 1 to 1 1 1 1 to 1 to 1 to 256 1 to 256 0 0 0 0 0 0
WRLR(1) WRSR(1) RDLR READ
FAST_READ Read Data Bytes at Higher Speed PW PP PE SSE(1) SE BE(1) DP RDP Page Write Page Program Page Erase SubSector Erase Sector Erase Bulk Erase Deep Power-down Release from Deep Power-down
1. Instruction available only in the T9HX process (see Important note on page 6).
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M25PE40
Instructions
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page Program (PP), Page Erase (PE), and Sector Erase (SE) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 7. Write Enable (WREN) instruction sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
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Instructions
M25PE40
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up Write Disable (WRDI) instruction completion Page Write (PW) instruction completion Page Program (PP) instruction completion Write Status Register (WRSR) instruction completion Write to Lock Register (WRLR) instruction completion Page Erase (PE) instruction completion SubSector Erase (SSE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Write Disable (WRDI) instruction sequence
S 0 C Instruction D High Impedance Q
AI03750D
Figure 8.
1
2
3
4
5
6
7
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M25PE40
Instructions
6.3
Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (80h), and the memory capacity of the device in the second byte (13h). Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 9 The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 6. Read Identification (RDID) Data-out sequence
Device identification Manufacturer identification Memory type 20h 80h Memory capacity 13h
Figure 9.
Read Identification (RDID) instruction sequence and Data-out sequence
S 0 C Instruction D Manufacturer Identification High Impedance Q MSB 15 14 13 MSB
AI06809b
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
Device Identification 3 2 1 0
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Instructions
M25PE40
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10. The status bits of the Status Register are as follows:
6.4.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.4.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write, Program or Erase instruction is accepted.
6.4.3
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3) becomes protected against Page Program (PP), Page Erase (PE), Sector Erase (SE) and SubSector Erase (SSE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if:

all Block Protect (BP2, BP1, BP0) bits are 0 the Lock Register protection bits are not all set (`1')
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. When the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits. In such a state, as the Write Status Register (WRSR) instruction is no longer accepted for execution, the definition of the size of the Write Protected area cannot be further modified. Table 7.
b7 SRWD 0 0 BP2 BP1 BP0 WEL
Status Register format(1) (2) (3)
b0 WIP
1. WEL (Write Enable Latch) and WIP ((Write In Program) are volatile read-only bits (WEL is set and reset by specific instructions; WIP is automatically set and reset by the internal logic of the device). 2. SRWD = Status Register Write Protect bit; BP0, BP1, BP2 = Block Protect Bits. 3. The BP bits and the SRWD bit exist only in the T9HX process.
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M25PE40
Instructions Figure 10. Read Status Register (RDSR) instruction sequence and Data-out sequence
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB
AI02031E
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register Out 6 5 4 3 2 1 0 7
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Instructions
M25PE40
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Note:
The Status Register BPi and SRWD bits are available in the in the T9HX process only. See Important note on page 6 for more details. Before the Write Status Register (WRSR) instruction can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the Status Register. b6 and b5 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal (see Section 6.4.4). If a Write Status Register (WRSR) instruction is interrupted by a Reset Low pulse, the internal cycle of the Write Status Register operation (whose duration is tW) is first completed (provided that the supply voltage VCC remains within the operating range). After that the device enters the Reset mode (see also Table 12: Device status after a Reset Low pulse and Table 22: Timings after a Reset Low pulse). Figure 11. Write Status Register (WRSR) instruction sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
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M25PE40 Table 8.
Instructions Protection modes (T9HX process only, see Important note on page 6)
Mode Write Protection of the Status Register Status Register is Writable (if the WREN instruction has set the WEL bit) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Memory Content Protected Area(1) Unprotected Area(1)
W SRWD Signal Bit 1 0 1 0 0 1
Second Software Protected (SPM2)
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
0
1
Status Register is Hardware Hardware write protected Protected The values in the SRWD, (HPM) BP2, BP1 and BP0 bits cannot be changed
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 3.
The protection features of the device are summarized in Table 8. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W):
If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM2) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM2), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used.
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Instructions
M25PE40
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Read Data Bytes (READ) instruction sequence and Data-out sequence
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
Instruction
24-Bit Address
23 22 21 MSB High Impedance
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI03748D
1. Address bits A23 to A19 are Don't Care.
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M25PE40
Instructions
6.7
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and Data-out sequence
S 0 C Instruction 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31
D High Impedance Q
23 22 21
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte
D
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
AI04006
Q
7 MSB
6
5
4
3
2
1. Address bits A23 to A19 are Don't Care.
29/60
Instructions
M25PE40
6.8
Note:
Read Lock Register (RDLR)
The Read Lock Register (RDLR) instruction is decoded only in the in the T9HX process (see Important note on page 6). The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector (or subsector). Each address bit is latched-in during the rising edge of Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 14. The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at any time during data output. Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Table 9.
Bit b7-b4 `1' b1 Sector Lock Down `0' `1' b0 Sector Write Lock `0'
Lock Registers
Bit Name Value Reserved The Write Lock and Lock Down Bits cannot be changed. Once a `1' is written to the Lock Down Bit it cannot be cleared to `0', except by a Reset or power-up. The Write Lock and Lock Down Bits can be changed by writing new values to them. (Default value). Write, Program and Erase operations in this sector will not be executed. The memory contents will not be changed. Write, Program and Erase operations in this sector are executed and will modify the sector contents. (Default value). Function
Figure 14. Read Lock Register (RDLR) instruction sequence and data-out Sequence
S 0 C Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D High Impedance Q
23 22 21 MSB
3
2
1
0 Lock Register Out 7 6 5 4 3 2 1 0
MSB
AI10783
30/60
M25PE40
Instructions
6.9
Page Write (PW)
The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Write (PW) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). The rest of the page remains unchanged if no power failure occurs during this write cycle. The Page Write (PW) instruction performs a page erase cycle even if only one byte is updated. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are written from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be written correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly written at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few bytes (see Table 20: AC characteristics (50 MHz operation, T9HX (0.11m) process)). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Write (PW) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Write cycle (whose duration is tPW) is initiated. While the Page Write cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Write cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Write (PW) instruction applied to a page that is Hardware Protected is not executed. Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
31/60
Instructions Figure 15. Page Write (PW) instruction sequence
M25PE40
S 0 C Instruction 24-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 Data Byte 3 Data Byte n
D
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
AI04045
1. Address bits A23 to A19 are Don't Care 2. 1 n 256
32/60
M25PE40
Instructions
6.10
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are programmed from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Table 19: AC characteristics (33 MHz operation)). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page that is Hardware Protected is not executed. Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
33/60
Instructions Figure 16. Page Program (PP) instruction sequence
M25PE40
S 0 C Instruction 24-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 Data Byte 3 Data Byte n
D
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
AI04044
1. Address bits A23 to A19 are Don't Care 2. 1 n 256
34/60
M25PE40
Instructions
6.11
Note:
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction is decoded only in the in the T9HX process (see Important note on page 6). The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes (pointing to any address in the targeted sector and one data byte on Serial Data Input (D). The instruction sequence is shown in Figure 17. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed. Lock Register bits are volatile, and therefore do not require time to be written. When the Write to Lock Register (WRLR) instruction has been successfully executed, the Write Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value. Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Write to Lock Register (WRLR) instruction sequence
S 0 C Instruction 24-Bit Address Lock Register Value 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
AI10784b
Table 10.
Lock Register In(1)
Sector Bit b7-b2 Value `0' Sector Lock Down Bit Value Sector Write Lock Bit Value
All sectors
b1 b0
1. The table rows in gray are true for products processed in the T7X process only (see Important note on page 6).
35/60
Instructions
M25PE40
6.12
Page Erase (PE)
The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data Input (D). Any address inside the Page is a valid address for the Page Erase (PE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 18. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Page Erase (PE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Erase cycle (whose duration is tPE) is initiated. While the Page Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Page Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Erase (PE) instruction applied to a page that is Hardware Protected is not executed. Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 18. Page Erase (PE) instruction sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI04046
1. Address bits A23 to A19 are Don't Care.
36/60
M25PE40
Instructions
6.13
Note:
SubSector Erase (SSE)
The SubSector Erase (SSE) instruction is decoded only in the in the T9HX process (see Important note on page 6). The SubSector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The SubSector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data Input (D). Any address inside the SubSector (see Table 4) is a valid address for the SubSector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 20. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the SubSector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed SubSector Erase cycle (whose duration is tSSE) is initiated. While the SubSector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed SubSector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A SubSector Erase (SSE) instruction applied to a subsector that contains a page that is Hardware or software Protected is not executed. Any SubSector Erase (SSE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. If Reset (Reset) is driven Low while a SubSector Erase (SSE) cycle is in progress, the SubSector Erase cycle is interrupted and data may not be erased correctly (see Table 12: Device status after a Reset Low pulse). On Reset going Low, the device enters the Reset mode and a time of tRHSL is then required before the device can be re-selected by driving Chip Select (S) Low. For the value of tRHSL see Table 22: Timings after a Reset Low pulse in Section 11: DC and AC parameters. Figure 19. SubSector Erase (SSE) instruction sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI12356
1. Address bits A23 to A19 are Don't Care.
37/60
Instructions
M25PE40
6.14
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data Input (D). Any address inside the Sector (see Table 4) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 20. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a sector that contains a page that is Hardware Protected is not executed. Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 20. Sector Erase (SE) instruction sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI03751D
1. Address bits A23 to A19 are Don't Care.
38/60
M25PE40
Instructions
6.15
Note:
Bulk Erase (BE)
The Bulk Erase (BE) instruction is decoded only in the in the T9HX process (see Important note on page 6). The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 21. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. Any Bulk Erase (BE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. A Bulk Erase (BE) instruction is ignored if at least one sector or subsector is write-protected (Hardware or Software protection). If Reset (Reset) is driven Low while a Bulk Erase (BE) cycle is in progress, the Bulk Erase cycle is interrupted and data may not be erased correctly (see Table 12: Device status after a Reset Low pulse). On Reset going Low, the device enters the Reset mode and a time of tRHSL is then required before the device can be re-selected by driving Chip Select (S) Low. For the value of tRHSL see Table 22: Timings after a Reset Low pulse in Section 11: DC and AC parameters. Figure 21. Bulk Erase (BE) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7
AI03752D
39/60
Instructions
M25PE40
6.16
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2, as specified in Table 17. Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. This releases the device from this mode. The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby Power mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 22. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 22. Deep Power-down (DP) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tDP
Stand-by Mode
Deep Power-down Mode
AI03753D
40/60
M25PE40
Instructions
6.17
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 23. The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the instruction to be rejected, and not executed. After Chip Select (S) has been driven High, followed by a delay, tRDP, the device is put in the Standby Power mode. Chip Select (S) must remain High at least until this period is over. The device waits to be selected, so that it can receive, decode and execute instructions. Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 23. Release from Deep Power-down (RDP) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tRDP
High Impedance Q Deep Power-down Mode Stand-by Mode
AI06807
41/60
Power-up and Power-down
M25PE40
7
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value:

VCC(min) at Power-up, and then for a further delay of tVSL VSS at Power-down
A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program (PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write, Program or Erase instructions should be sent until the later of:

tPUW after VCC passed the VWI threshold tVSL after VCC passed the VCC(min) level
These values are specified in Table 11 If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration of the Power-up and Power-down phases. At Power-up, the device is in the following state:

The device is in the Standby Power mode (not the Deep Power-down mode) The Write Enable Latch (WEL) bit is reset The Write In Progress (WIP) bit is reset The Lock Registers are reset (Write Lock bit, Lock Down bit) = (0, 0)
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 100 nF). At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)
42/60
M25PE40 Figure 24. Power-up timing
VCC VCC(max) Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed VCC(min) Reset State of the Device VWI tPUW tVSL Read Access allowed
Power-up and Power-down
Device fully accessible
time
AI04009C
Table 11.
Symbol tVSL(1) tPUW(1) VWI(1)
Power-up timing and VWI threshold
Parameter VCC(min) to S low Time delay before the first Write, Program or Erase instruction Write Inhibit Voltage Min. 30 1 1.5 10 2.5 Max. Unit s ms V
1. These parameters are characterized only, over the temperature range -40C to +85C.
43/60
Reset
M25PE40
8
Reset
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. All the Lock bits are reset to 0 after a Reset Low pulse. Table 12 shows the status of the device after a Reset Low pulse. Table 12. Device status after a Reset Low pulse
Conditions: Reset pulse occurred While decoding an instruction(1): WREN, WRDI, RDID, RDSR, READ, RDLR, Fast_Read, WRLR, PW, PP, PE, SE, BE, SSE, DP, RDP Under completion of an Erase or Program cycle of a PW, PP, PE, SSE, SE, BE operation Under completion of a WRSR operation Device deselected (S High) and in Standby mode
1. S remains Low while Reset is Low.
Lock bits status
Internal logic status
Addressed data
Reset to 0
Same as POR
Not significant
Reset to 0
Equivalent to POR Equivalent to POR (after tW) Same as POR
Addressed data could be modified Write is correctly completed Not significant
Reset to 0 Reset to 0
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M25PE40
Initial delivery state
9
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). All usable Status Register bits are 0.
10
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 13.
Symbol TSTG TLEAD VIO VCC VESD Storage temperature Lead temperature during soldering Input and Output Voltage (with respect to Ground) Supply Voltage Electrostatic Discharge Voltage (human body model)(2)
Absolute maximum ratings
Parameter Min. -65 Max. 150 Unit C C V V V
See note (1) -0.6 -0.6 -2000 VCC + 0.6 4.0 2000
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ).
45/60
DC and AC parameters
M25PE40
11
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 14.
Symbol VCC TA Supply Voltage Ambient Operating Temperature
Operating conditions
Parameter Min. 2.7 -40 Max. 3.6 85 Unit V C
Table 15.
Symbol CL
Measurement conditions(1)
Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages Min. 30 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 25. AC measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 16.
Symbol COUT CIN
Capacitance(1)
Parameter Output Capacitance (Q) Input Capacitance (other pins) Test Condition VOUT = 0V VIN = 0V Min. Max. 8 6 Unit pF pF
1. Sampled only, not 100% tested, at TA=25C and a frequency of 20 MHz.
46/60
M25PE40 Table 17.
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 ICC5 VIL VIH VOL VOH
DC and AC parameters DC characteristics
Parameter Input Leakage Current Output Leakage Current Standby Current (Standby and Reset modes) Deep Power-down Current Operating Current (FAST_READ) Operating Current (PW) Operating Current (SE) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA IOH = -100 A VCC-0.2 S = VCC, VIN = VSS or VCC S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open C = 0.1VCC / 0.9.VCC at 50 MHz, Q = open S = VCC S = VCC - 0.5 0.7VCC Test condition (in addition to those in Table 14) Min. Max. 2 2 50 10 6 8 15 15 0.3VCC VCC+0.4 0.4 Unit A A A A mA mA mA mA V V V V
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DC and AC parameters Table 18. AC characteristics (25 MHz operation)
Test conditions specified in Table 14 and Table 15 Symbol fC fR tCH tCL
(1) (1)
M
M25PE40
Alt. fC
Parameter Clock Frequency for the following instructions: FAST_READ, PW, PP, PE, SE, DP, RDP, WREN, WRDI, RDSR Clock Frequency for READ instructions
Min. D.C. D.C. 18 18 0.1 10 10 5 5 10 10 100
Typ.
Max. 25 20
Unit MHz MHz ns ns V/ns ns ns ns ns ns ns ns
tCLH tCLL
Clock High Time Clock Low Time Clock Slew Rate 2 (peak-to-peak)
tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ (2) tCLQV tCLQX tTHSL tSHTL tDP
(2) (2)
tCSS
S Active Setup Time (relative to C) S Not Active Hold Time (relative to C)
tDSU tDH
Data In Setup Time Data In Hold Time S Active Hold Time (relative to C) S Not Active Setup Time (relative to C)
tCSH tDIS tV tHO
S Deselect Time Output Disable Time Clock Low to Output Valid Output Hold Time Top Sector Lock Setup Time Top Sector Lock Hold Time S to Deep Power-down S High to Standby Power mode Page Write Cycle Time (256 bytes)
15 15 0 50 100 3 30 11 10.2+ n*0.8/256 1.2 0.4+ n*0.8/256 10 1 5 25
ns ns ns ns ns s s ms
tRDP tPW
(3)
Page Write Cycle Time (n bytes) Page Program Cycle Time (256 bytes)
tPP (3) tPE tSE
ms
Page Program Cycle Time (n bytes) Page Erase Cycle Time Sector Erase Cycle Time
20 5
ms s
1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256)
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M25PE40 Table 19. AC characteristics (33 MHz operation)
DC and AC parameters
33MHz only available for products marked since week 40 of 2005(1) Test conditions specified in Table 14 and Table 15 Symbol fC fR tCH
(2)
Alt. fC
Parameter Clock Frequency for the following instructions: FAST_READ, PW, PP, PE, SE, DP, RDP, WREN, WRDI, RDSR Clock Frequency for READ instructions
Min. D.C. D.C. 13 13
Typ.
Max. 33 20
Unit MHz MHz ns ns V/ns ns ns ns ns ns ns ns
tCLH tCLL
Clock High Time Clock Low Time Clock Slew Rate 2 (peak to peak)
tCL (2)
0.1 10 10 3 5 5 5 100 12 12 0 50 100 3 30 11 10.2+ n*0.8/256 1.2 0.4+ n*0.8/256 10 1 5 25
tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ
(3)
tCSS
S Active Setup Time (relative to C) S Not Active Hold Time (relative to C)
tDSU tDH
Data In Setup Time Data In Hold Time S Active Hold Time (relative to C) S Not Active Setup Time (relative to C)
tCSH tDIS tV tHO
S Deselect Time Output Disable Time Clock Low to Output Valid Output Hold Time Top Sector Lock Setup Time Top Sector Lock Hold Time S to Deep Power-down S High to Standby Power mode Page Write Cycle Time (256 bytes)
ns ns ns ns ns s s ms
tCLQV tCLQX tTHSL tSHTL tDP
(3) (3)
tRDP
tPW (4)
Page Write Cycle Time (n bytes) Page Program Cycle Time (256 bytes)
tPP (4) tPE tSE
ms
Page Program Cycle Time (n bytes) Page Erase Cycle Time Sector Erase Cycle Time
20 5
ms s
1. Details of how to find the date of marking are given in Application Note, AN1995. 2. tCH + tCL must be greater than or equal to 1/ fC 3. Value guaranteed by characterization, not 100% tested in production. 4. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256)
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DC and AC parameters Table 20. AC characteristics (50 MHz operation, T9HX (0.11m) process(1))(2) (3)
Test conditions specified in Table 14 and Table 15 Symbol fC fR tCH(4) tCL(4) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(5) tCLQV tCLQX tWHSL tSHWL
(6) (6)
M25PE40
Alt. fC
Parameter Clock Frequency for the following instructions: FAST_READ, RDLR, PW, PP, WRLR, PE, SE, SSE, DP, RDP, WREN, WRDI, RDSR, WRSR Clock Frequency for READ instructions
Min. D.C. D.C. 9 9
Typ.
Max. 50 33
Unit MHz MHz ns ns V/ns ns ns ns ns ns ns ns
tCLH tCLL tCSS tDSU tDH
Clock High Time Clock Low Time Clock Slew Rate (peak to peak) S Active Setup Time (relative to C) S Not Active Hold Time (relative to C) Data In Setup Time Data In Hold Time S Active Hold Time (relative to C) S Not Active Setup Time (relative to C)
2
0.1 5 5 2 5 5 5 100 8 8 0 50 100 3 30 3 11 0.8 int(n/8) x 0.025(8) 10 1 40 5 15 23 3 20 5 150 10
tCSH tDIS tV tHO
S Deselect Time Output Disable Time Clock Low to Output Valid Output Hold Time Write Protect Setup Time Write Protect Hold Time S to Deep Power-down S High to Standby Mode Write Status Register Cycle Time Page Write Cycle Time (256 bytes) Page Program Cycle Time (256 bytes) Page Program Cycle Time (n bytes) Page Erase Cycle Time Sector Erase Cycle Time SubSector Erase Cycle Time Bulk Erase Cycle Time
ns ns ns ns ns s s ms ms ms ms s ms s
tDP(5) tRDP(5) tW tPW(7) tPP(7) tPE tSE tSSE tBE
2. Preliminary data.
1. See Important note on page 6.
3. Details of how to find the Technology Process in the marking are given in AN1995, see also Section 13: Part numbering. 4. tCH + tCL must be greater than or equal to 1/ fC 5. Value guaranteed by characterization, not 100% tested in production. 6. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 7. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 n 256). 8. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
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M25PE40 Figure 26. Serial input timing
DC and AC parameters
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
Figure 27. Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold timing
TSL or W tTHSL tWHSL S tSHTL tSHWL
C
D High Impedance Q
AI3559
1. For the differences between devices produced in the two processes, see Important note on page 6.
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DC and AC parameters Figure 28. Output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
M25PE40
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449e
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M25PE40 Table 21. Reset conditions
DC and AC parameters
Test conditions specified in Table 14 and Table 15 Symbol tRLRH(1) tSHRH Alt. tRST Parameter Reset Pulse Width Chip Select High to Reset High Chip should have been deselected before Reset is de-asserted Conditions Min. 10 10 Typ. Max. Unit s ns
1. Value guaranteed by characterization, not 100% tested in production.
Table 22.
Timings after a Reset Low pulse(1)(2)
Test conditions specified in Table 14 and Table 15
Symbol Alt.
Parameter
Conditions: Reset pulse occurred While decoding an instruction(3): WREN, WRDI, RDID, RDSR, READ, RDLR, Fast_Read, WRLR, PW, PP, PE, SE, BE, SSE, DP, RDP
Max.
Unit
30
s
tRHSL
tREC
Reset Recovery Time
Under completion of an Erase or Program cycle of a PW, PP, PE, SE, BE operation Under completion of an Erase cycle of an SSE operation Under completion of a WRSR operation Device deselected (S High) and in Standby mode
300 3 tW (see Table 20) 0
s ms ms s
1. All the values are guaranteed by characterization, and not 100% tested in production. 2. See Table 12 for a description of the device status after a Reset Low pulse. 3. S remains Low while Reset is Low.
Figure 29. Reset AC waveforms
S
tSHRH tRLRH
tRHSL
Reset
AI06808
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Package mechanical
M25PE40
12
Package mechanical
Figure 30. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead 6 x 5 mm, package outline
A R1 D1 B
MCAB bbb 70-ME
D
aaa C A
E
E1
E2
e
2x
0.10 C B aaa C B 0.10 C A
b A2 D2 L
ddd
A
A1 A3
C
1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1.
Table 23.
VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead 6 x 5 mm, package mechanical data
millimeters inches Max 1.00 0.05 0.0256 0.0079 0.35 0.48 0.0157 0.2362 0.2264 3.20 3.60 0.1339 0.1969 0.1870 3.80 - 0.00 0.50 0.75 12 0.15 0.10 0.05 4.30 - 0.1575 0.0500 0.0039 0.0236 0.1496 - 0.0000 0.0197 0.0295 12 0.0059 0.0039 0.0020 0.1693 - 0.1260 0.1417 0.0138 0.0189 Typ 0.0335 Min 0.0315 0.0000 Max 0.0394 0.0020
Symbol Typ A A1 A2 A3 b D D1 D2 E E1 E2 e R1 L aaa bbb ddd 0.65 0.20 0.40 6.00 5.75 3.40 5.00 4.75 4.00 1.27 0.10 0.60 0.85 Min 0.80 0.00
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M25PE40
Package mechanical Figure 31. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 24.
SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data
millimeters inches Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 1.04 5.00 6.20 4.00 - 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 - 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 - 0.020 8 0.050 Typ Min Max 0.069 0.010
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
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Package mechanical
M25PE40
Figure 32. SO8W - 8 lead Plastic Small Outline, 208 mils body width, package outline
A2 b e D
A c CP
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 25.
SO8W - 8 lead Plastic Small Outline, 208 mils body width, package mechanical data
millimeters inches Max 2.50 0.00 1.51 0.40 0.20 0.35 0.10 0.25 2.00 0.51 0.35 0.10 6.05 5.02 7.62 1.27 - 0 0.50 8 6.22 8.89 - 10 0.80 0.050 0.198 0.300 - 0 0.020 8 0.016 0.008 0.000 0.059 0.014 0.004 Typ Min Max 0.098 0.010 0.079 0.020 0.014 0.004 0.238 0.245 0.350 - 10 0.031
Symbol Typ A A1 A2 b c CP D E E1 e k L N Min
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M25PE40
Part numbering
13
Part numbering
Table 26.
Example:
Ordering information scheme
M25PE40 V MP 6 T G
Device Type M25PE = Page-Erasable Serial Flash memory
Device Function 40 = 4 Mbit (512Kb x 8)
Operating Voltage V = VCC = 2.7 to 3.6 V
Package MW = SO8W (208 mils width) MP = VFQFPN8 6 x 5 mm (MLP8) MN = SO8N (150 mils width)(1)
Device Grade 6 = Industrial: device tested with standard test flow over -40 to 85 C
Option blank = Standard Packing T = Tape and Reel Packing
Plating Technology P or G = ECOPACK(R) (RoHS compliant)
1. Package only available for products in the T9HX process.
Note:
For a list of available options (speed, package, etc.), for further information on any aspect of this device or when ordering parts operating at 50 MHz (0.11 m, process digit `4'), please contact your nearest ST Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
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Revision history
M25PE40
14
Revision history
Table 27.
Date 01-Apr-2004
Document revision history
Revision 0.1 Document written Write Protect (W) pin replaced by Top Block Lock (TBL). Section 2.5: Reset (Reset) description modified. JEDEC signature modified. Reset timings tRLRH, tRHSL and tSHRH removed from Table 19: AC characteristics (33 MHz operation) and inserted in Table 21: Reset timings (tRHSL modified). Document status promoted from Target Specification to Preliminary Data. Top Block Lock (TBL) renamed as Top Sector Lock (TSL). Small text changes. Deep Power-Down mode clarified in Section 4.6: Active Power, Standby Power and Deep Power-down modes. Notes removed from Table 26: Ordering information scheme. Wording changes. SO16 package removed, SO8 Wide package added. Added Table 19: AC characteristics (33 MHz operation). Document status promoted from Preliminary Data to Datasheet. Table 18: AC characteristics (25 MHz operation)updated. Section 4.2: An easy way to modify data, Section 4.3: A fast way to modify data, Section 6.9: Page Write (PW) and Section 6.10: Page Program (PP) updated to explain optimal use of Page Write and Page Program instructions. Clock slew rate changed from 0.03 to 0.1 V/ns. Updated Table 26: Ordering information scheme. Added Ecopack(R) information. Changed document to new template; amended figure in Feature summary; replaced Figure 4: Bus master and memory devices on the SPI bus; amended data in Table 18 and Table 19; amended title of Figure 30: VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead 6 x 5 mm, package outline and added a footnote; amended name of the MP package in Table 26: Ordering information scheme Changes
09-Nov-2004
1.0
01-Dec-2004
2.0
11-Jan-2005
3.0
4-Oct-2005
4.0
11-Aug 2006
5
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M25PE40 Table 27.
Date
Revision history Document revision history
Revision Changes 50 MHz frequency added. SO8N package added, VFQFPN and SO8W package specifications updated (see Section 12: Package mechanical). The sectors are further divided up into subsectors (see Table 4: Memory organization). Important note on page 6 added. Figure 4: Bus master and memory devices on the SPI bus updated and explanatory paragraph added. VCC supply voltage and VSS ground added. Section 4.8: Protection modes modified. Section 8: Reset added, Reset timings table split into Table 21: Reset conditions and Table 22: Timings after a Reset Low pulse. At Power-up the WIP bit is reset (see Section 7: Power-up and Power-down). VIO max changed in Table 13: Absolute maximum ratings. End timing line of tSHQZ moved in Figure 28: Output timing. products processed in T9HX process added to datasheet: - WP pin replaces TSL (T7X technology), see Section 2.6: Write Protect (W) or Top Sector Lock (TSL) - Write Status Register (WRSR) and SubSector Erase (SSE) instructions added for T9HX process - subsector protection granularity removed in T9HX process, still exists in T7X process - Table 4: Memory organization updated to show subsectors - Status Register BP2, BP1, BP0 bits and SRWD bit added. Small text changes. T7X process name corrected. Write Enable Latch (WEL) bit is reset also on completion of the SubSector Erase, Bulk Erase, Write to Lock Register and Write Status Register instructions (see Section 6.2: Write Disable (WRDI)). Address bit A20 is not Don't Care (Note 1 modified) in the Sector Erase (SE) instruction sequence.. SO8N package is only available in products manufactured in the T9HX process.
15-Jan-2007
6
23-Jan-2007
7
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M25PE40
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